The present invention relates generally to the field of processors and in particular to a method of flushing uncommitted instructions from a processor execution pipeline in response to a branch misprediction.
Microprocessors perform computational tasks in a wide variety of applications. Improved processor performance is almost always desirable, to allow for faster operation and/or increased functionality through software changes. In many embedded applications, such as portable electronic devices, conserving power is also an important consideration in processor design and implementation.
Most modern processors employ a pipelined architecture, where sequential instructions, each having multiple execution steps, are overlapped in execution. For maximum performance, the instructions should flow through continuously through the pipeline. However, instructions often become stalled in the pipeline for a variety of reasons, such as data dependencies between instructions, delays associated with memory accesses, an inability to allocate sufficient pipeline resources to instructions, and the like. Minimizing pipeline stalls and resolving them efficiently are important factors in achieving improved processor performance.
Real-world programs include conditional branch instructions, the actual branching behavior of which is commonly not known until the instruction is evaluated deep in the pipeline. Commonly modern processors employ various forms of branch prediction, whereby the branching behavior of conditional branch instructions is predicted early in the pipeline, and the processor speculatively allocates pipeline resources, and/or fetches and speculatively executes instructions, based on the branch prediction. When the actual branch behavior is determined, if the branch was mispredicted, the speculatively fetched instructions must be flushed from the pipeline, and new instructions fetched from the correct branch target address. Mispredicted branches adversely impact processor performance and power consumption.
Commonly, in handling a mispredicted branch instruction, all instructions older than the branch instruction—that is, the instructions that entered the pipeline ahead of the branch instruction—are allowed to complete execution before the speculatively fetched instructions are flushed. Where one or more of the older instructions is stalled in the pipeline due to a long latency operation, waiting for the dependency to be resolved before flushing the pipeline exacerbates the mispredicted branch performance penalty.